The present invention relates to a semiconductor device and, more particularly, to a technique which is effectively applied to constitution of a sense amplifier section or/and a differential amplifier section in the semiconductor device.
The list of reference documents which are referred to in the present invention is as follows. The reference documents will be indicated by document numbers.
(1) [Reference Document 1]: VLSI Memory Chip Design, Kiyoo Itoh, Springer Series in Advanced Microelectronics, pp. 223-230
(2) [Reference Document 2]: Fundamental of Modern VLSI Devices, Cambridge University Press 1998
(3) [Reference Document 3]: Japanese Patent Laid-Open No. 8-167661
(4) [Reference Document 4]: Japanese Patent Laid-Open No. 2000-196017
As a technique examined by the present inventors, the following technique has been thought about the configuration of the sense amplifier section in the semiconductor device. Although the following technique has not been a known technique, this technique is examined by the present inventors as the assumption of the present invention. The outline of the technique will be described with reference to the drawings. FIG. 16A shows a layout diagram of a transistor channel region and a sense amplifier in a DRAM chip examined by the present inventors. FIG. 16B shows a layout diagram of a sense amplifier cross coupling section serving as a main part of the sense amplifier. FIG. 16C shows a sectional view of the sense amplifier cross coupling section. FIG. 17 shows a circuit diagram of each part of the sense amplifier cross coupling section and common source lines.
In a DRAM (Dynamic Random Access Memory), in order to reduce the cost and simplify the processes thereof, N+-type polysilicon has been used as each gate material of PMOS and NMOS transistors. In the DRAM, an impurity density of a channel region PINP(SA) of an NMOS transistor of a sense amplifier block SAB in a memory array MA is constant at a density of p(SA). Similarly, an impurity density of a channel region NINP(SA) of a PMOS transistor of a sense amplifier block SAB in a memory array MA is constant at a density of n(SA). Each of the densities is equal to an impurity density p(peri) of a channel region PINP(peri) of an NMOS transistor in a peripheral circuit peri and an impurity density n(peri) of a channel region NINP(peri) of a PMOS transistor in the peripheral circuit peri.
In addition, transistors of a sense amplifier cross coupling section CC comprise PMOS transistors (to be referred to N+-type gate PMOS hereinafter) Qp0xe2x80x2 and Qp1xe2x80x2 of N+-type polysilicon gates N+poly each using an N+-type polysilicon layer as a gate as shown in FIGS. 16B and 16C and FIG. 17, and NMOS transistors (to be referred to as N+-type gate NMOS hereinafter) Qn0 and Qn1 of N+-type polysilicon gates N+poly each using an N+-type polysilicon layer as a gate. Each transistor of the N+-type gate PMOSs Qp0xe2x80x2 and Qp1xe2x80x2 has a buried channel structure and has such a problem that deviation of threshold voltage increases. Influence of threshold voltage deviation of a pair of transistors on the sense amplifier has been described in [Reference Document 1] in detail. Threshold voltage difference between a pair of MOSs and generated by deviation of the threshold voltage causes a read error since reducing an effective signal voltage in a sense amplifier operation. The threshold voltage deviation of this transistor is caused by deviation of process steps, layouts, or the like. In order to reduce this threshold voltage deviation, the configuration described above has used a transistor having a relatively large gate in length, or/and adopted patterns having fewer deviation in layouts.
As a result of consideration of the present inventor, the following has been apparent from the technique of the semiconductor devices described above. For example, as micro fabrication of semiconductor devices develops, a sufficient effect on reduction of the threshold voltage deviation has not been objected by the above-mentioned technique only. In FIG. 17 described above, each of the N+-type gate PMOS Qp0xe2x80x2 and Qp1xe2x80x2 has a channel structure of a buried channel, and so the threshold voltage deviation thereof increases. In addition, since N+-type gate NMOS Qn0 and Qn1 use N+-type polysilicon layers as gates and comes to surface channels, it has smaller threshold voltage deviation than the N+-type gate PMOS. However, even the transistors of the surface channels are required to reduce both memory array and layout size of the sense amplifier by micro fabrication, and so layouts each having fewer deviation and small area have been difficult to realize.
Further, there is threshold voltage deviation caused by a step of channel impurity implantation (to be referred to as channel implantation hereinafter) for adjusting each threshold voltage of transistors, so that total amounts of deviation come to about several tens mV to a hundred and several tens mV or more. This results in reduction in effective signals sensed actually by sense amplifiers, and in high probability of read errors of sense amplifiers, and in increase in the number of fail bits. In addition, in a highly integrated and large-capacity DRAM, a data line swing voltage is made lower and capacity of memory cells decreases due to structure thereof, so that the read out signal voltage from memory cell decreases. Therefore, in order to achieve stable operation thereof, it is essential that the threshold voltage deviation is reduced.
Thereupon, an object of the present invention is to reduce the difference between threshold voltages of sense amplifier transistors for decreasing signal voltages, and to provide sense amplifiers having reduced vth deviation, which lessen influence of the transistor threshold voltage deviation that is one of noise elements when the sense amplifiers are amplified, and which are capable of accurately sensing and amplifying micro signals having read from the memory cells in the sense amplifiers.
The above and other objects and novel features of the present invention will be apparent from the description of the present specification and the accompanying drawings.
Of inventions disclosed in this application, the outlines of typical ones will be described below.
According to the present invention, in order to reduce deviations of threshold voltages caused by an amount of channel impurity implantation of channel (to be referred to as an amount of channel implantation) for adjusting threshold voltages, the amount of channel implantation in the steps of fabricating transistors, and the deviations of threshold voltage are reduced, and a sense amplifier having a small threshold voltage difference therebetween is realized. In addition, if there is such a threshold voltage that a leakage current is worth consideration is generated, then a substrate bias voltage is used to compensate for decrease in threshold voltage, and a sense amplifier which has a small power consumption and which achieves a small deviation of threshold voltage is realized.
More specifically, a semiconductor device according to the present invention is one that comprises a plurality of memory cells arranged at intersecting points of a plurality of word lines and a plurality of data lines; a plurality of sense amplifiers provided so as to each correspond to said plurality of data lines and having a first MISFET pair of a first conductivity type which uses a cross-coupled P-type polysilicon layer as a gate electrode; and a decoder circuit having a second MISFET of said first conductivity type which uses a P-type polysilicon layer as a gate electrode and which selects any one of said memory cells, wherein an impurity density of channel of said first MISFET pair is lower than that of said second MISFET.
Further, another semiconductor device according to the present invention comprises a circuit that includes a first MISFET of a first conductivity type in which a substrate potential is used as a first potential and which uses a P-type polysilicon layer as a gate electrode, and a second MISFET of a second conductivity type in which a second potential is used as a substrate potential and which uses an N-type polysilicon layer as a gate electrode; a third and fourth MISFETs of said first conductivity type which use P-type polysilicon layers as gate electrodes and whose the gate electrodes are connected to any one of drain terminals thereof and whose source terminals are common to each other; a fifth MISFET of said second conductivity type which uses an N-type polysilicon layer as a gate electrode and the gate electrode of which a first signal is input into and a drain terminal of which is connected to a drain terminal of said third MISFET; and a sixth MISFET of said second conductivity type which use an N-type polysilicon layer as a gate electrode and the gate electrode of which a second signal is input into and a source terminal whose is commonly connected to said fifth MISFET, wherein each impurity density of channels of said fifth MISFET and said sixth MISFET is lower than that channel of the first MISFET, and wherein each substrate potential of said fifth MISFET and said sixth MISFET is lower than said second potential.